1. Field of the Invention
The invention relates to a device for multiplying a first number, comprising a first plurality of m.n binary digits, by a second number comprising a second plurality of p.s binary digits. The device comprises a first array of partial product forming devices having inputs for receiving the first and second numbers and outputs connected to inputs of a sum forming device for transferring a third plurality of q partial products to the sum forming device. The sum forming device comprises means for forming a complete sum of the said q partial products with respect to their relative significance levels, the complete sum appearing on an output of the device for further use. In certain types of data processing systems there exists a substantial need for fast devices for performing multiplications on a multiplicand and a multiplier which may each consist of a large number of bits. Such a need may exist in a computer which is used for scientific purposes and which must perform a large number of successive multiplications in an iterating manner, or, multiplications between sets of quantities to be multiplied pair-wise. On the other hand, operations of this kind also occur in large computers for accounting purposes or in special purpose computers, such as computers for performing cross-correlations or auto-correlations on complex series of measurements. A further application can be found in digital transversal filters.
2. Description of the Prior Art
Generally, decimal multiplication is performed by the successive addition of performed multiples (1x . . . 9x) of the multiplicand. Similarly, binary multiplication is usually performed by the successive shifting of the multiplicand relative to a developing preliminary product, while the values of the successive multiplier bits determine whether or not the multiplicand must be added to the preliminary product. It is known to speed up the multiplication by performing the operations in parallel. The article R. H. Larson, "Medium Speed Multiply", IBM Technical Disclosure Bulletin 16, (Dec. 1973), discloses a common bus having a capacity of four bits, being used for applying four multiplier bits in parallel. Consequently, the known device has a cyclic mode of operation which must be repeated a number of times for each complete multiplication. Moreover, the known device requires an adder involving complex propagation of the carry signals.